1. Field
Circuit devices and methods for forming circuit devices.
2. Background
A metal oxide semiconductor field effect transistor (MOSFET) is a common element of an integrated circuit such as a microprocessor or other circuit. The transistor typically includes a source and drain junction region formed in a semiconductor substrate and a gate electrode formed on a surface of the substrate. A gate length is generally the distance between the source and drain junction region. Within the substrate, the region of the substrate beneath the gate electrode and between the source and drain junctions is generally referred to as a channel with a channel length being the distance between the source and drain junctions.
A transistor device works generally in the following way. Carriers (e.g., electrons, holes) flow between source junction and drain junction by the establishment of contacts to the source and drain regions. In order to establish the carrier flow, a voltage is applied to the gate electrode to form an inversion layer of carriers in the channel. The minimum amount of gate voltage is generally referred to as a threshold voltage (Vt).
As noted above, many transistor devices are formed in a semiconductor substrate. The substrate body may be a bulk silicon substrate or a silicon on insulator (SOI) substrate. To form ohmic contacts to carriers in the channel, dopants are introduced (e.g., via ion implantation) into the substrate. Representatively, an N-type transistor device may have source and drain regions (and gate electrode) doped with an N-type dopant such as arsenic or phosphorous. The N-type regions are formed in a well that has previously been formed in the semiconductor substrate as a P-type conductivity. A suitable P-type dopant is boron.
The silicon and SOI body described above are designed to be fully depleted (i.e., removing of essentially all bulk charge carriers by an electric field). Fully depleted FET transistors tend to have better gate control on a channel potential than planar MOSFET devices at low drain bias VDS. Full depletion however, does not ensure better short-channel effects (SCEs) at high VDS as the drain electric field can reach the source end through the substrate in bulk silicon wafers or through a buried oxide (BOX) layer in SOI wafers. In general, it is desired that SCEs are low such that the transistor off-state leakage current, IOFF, (i.e., a current flowing between source and drain regions when a transistor is in an off state) remains as low as possible. SCEs may be determined by monitoring the subthreshold slope (SS) and drain induced barrier lowering (DIBL). Subthreshold slope, which is a measure of the gate coupling to the channel potential, is defined as SS=dVG/d[logIDS], where VG is the gate voltage and IDS is the drain-to-source current. DIBL, which is a measure of the threshold voltage shift versus drain bias, is defined as DIBL=(VTLIN−VTSAT)/(VDSAT−VDLIN). VTLIN is the linear threshold voltage at low drain bias VDLIN, typically 50 mV. VTSAT is the saturate threshold voltage at high drain bias VDSAT, which is typically in the range of from 1 to 1.2V for current generation of logic transistors. A steeper SS and/or reduced DIBL shift indicates lower IOFF.
Reduced drain-to-source coupling leads to better SCEs. Drain field penetration (i.e., drain-to-source coupling), may be reduced by scaling the substrate body size (e.g., thin body width WSI for double-gated transistors such as FinFETs, and thin TSI and WSI for triple-gated transistors such as tri-gates) or by introducing heavy doping in the source tip to channel and channel to drain tip junctions of bulk Si wafers or the Si body in SOI wafers. Very small body dimensions, however, are not desirable because of a potential for large external resistance (REXT).
In addition, heavy doping in the source tip to channel and channel to drain tip junctions is generally achieved by locally implanted dopants (P-type in N-type metal oxide semiconductor FETs (NMOSFETs) and N-type dopants in P-type metal oxide semiconductor FETs (PMOSFETs) introduced in the substrate body and in the case of the SOI substrate, in the Si body. Such implants are referred to as “halo” implants. Typical halo implants for NMOSFETs include boron and indium (In)). Halo implants for PMOSFETs include arsenic (As), antimony (Sb), and phosphorous (P). These halos are typically implanted at an angle resulting in potential overlap between the halos and source/drain (S/D) regions and/or tip regions. These Halo implant are more difficult to implement in a nonplanar FINFET or TRI-Gate configuration.